Design of CMOS Four-Quadrant Voltage Signal Multiplier Circuit Using Square Technique
Chaiwat Sakul ^*
Department of Technology, Faculty of Engineering and Technology, Rajamangalar University of Technolofy Srivijaya, Trang campus.

Abstract

This article presents a design of CMOS voltage signal multiplier circuit using square technique. The operation principle of the circuit based on characteristic of NMOS and PMOS operate in saturation region. The realization method is based on the square-law characteristic. The proposed circuit operates in voltage mode. It operates with ±1.2V power supply. The circuit has lost total power dissipation 0.62 mW. The performances and simulation results of the circuit are discussed in detail and demonstrated by PSpice simulation program.